VinRZ5110 32-bit RISC CPU

VinRZ5110 is a low power, high performance 32-bit processor solution targeting embedded applications where low power and system cost are of utmost importance. It is based on Harvard architecture, with single cycle memory access and multiple enhanced features as described below.

Key Enhanced Features

Five operating modes with optimized shadow register bank structure    -  Supports very fast context switching for high priority interrupt modes

Single cycle 32X16 MAC enabling convergence of RISC and DSP    -  Enables DSP applications

Native bus interface support for on-chip peripherals    -  Realizes low interrupt latencies

Memory copy, atomic memory access, semaphore instructions    -  Improves code density by a large margin

Low Power Modes support    -  Power-down mode (triggered by en_idle instruction)    -  Supports low power modes that facilitate CE designs

This processor system enables SoC designers to concentrate on design issues unique to their system. VinRZ5110 is a technology independent synthesizable macro, highly portable across processes and can be easily integrated into system-on-chip designs.

Processor Highlights

Technology Independent synthesizable soft core

Includes 32-bit, 5-stage Pipelined RISC CPU VinRCPU32

Support for DSP instructions    -  Saturated Addition    -  Saturated Subtraction    -  Integer Multiply    -  Multiply-accumulate

Byte, bit reversal instructions    -  Achieves faster bit manipulation times- advantageous for mobile applications

Immediate branch instruction with single cycle penalty

3-level fixed priority asynchronous Vectored Interrupt scheme

Single cycle instruction & data memory access

Support for up to 8 auxiliary processors

Support for external interrupt controller

AHB compliant System Bus Interface

VinRZ5110 comprises the VinRCPU32 Core, Single cycle access Instruction and Data Memory (SCAM) controllers, system control unit (SCU), external Auxiliary processor (AXP) interface and the System Bus Interface (SBI).

VinRCPU32 Core

The 32-bit RISC CPU core features a 32x16 bit MAC capable of single cycle MAC operations, which enhances execution times of DSP instructions that are critical to DSP applications. The 32 bit datapath has been designed to minimize data, branch and structural hazard-related stalls. It can operate in five operating modes and has a shadow register bank, that provides fast context switching for high priority interrupts.  
 
Click the below link to download the VinRZ5110 Product Brief;
http://vinchip.com/Product_Brief/VRZ5110.pdf 
 

VinRZ Tool Chain

VinRZ Tool Chain comprises the GCC 4.3.2 compiler, binutils 2.19 assembler, linker and gdb 6.8 Debugger. To improve the programming efficiency, it also includes ANSI C runtime library (libc.a) and C mathematical subroutine library (libm.a).

GDB (vinrz-elf-gdb) offers extensive facilities for tracing and altering the execution of application programs. The user can monitor and modify the values of programa€?s internal variables, and even call functions independent of the program's normal behavior.

Instruction Set Simulator VinRZ-iss is the simulation model,Rolex Replica Watches coded in high-level C programming language that executes programs written for the VinRZ target at a speed of 18 MIPS. This enables programmers to debug application code fast and early in the development cycle.

OpenOCD is an open-source on-chip debug solution for VinRZ target via JTAG port. It enables source level debugging with the standard GDB compiled for the VinRZ architecture. In addition, it supports internal and external FLASH memory programming.

VinRZ tool chain, VinRZ-iss Simulator and OpenOCD have been integrated into Eclipse IDE providing the industry standard Integrated Development Environment.

The following table depicts the collection of VinRZ tools and their description. Patek Philippe Replica

Tool Name	Tool Description
vinrz-elf-gcc	C cross compiler for producing vinrz assembly code.
vinrz-elf-as	Assembler for producing vinrz machine code.
vinrz-elf-ld	Linker to link VinRZ object modules together.
vinrz-elf-size	Displays information such as amount of FLASH or RAM taken by VinRZ object files.
vinrz-elf-nm	Extracts symbol table from an object file, similar to a map file.
vinrz-elf-objdump	Displays, extracts, or copies information from many VinRZ object file formats.
vinrz-elf-objcopy	Copies or extracts parts of VinRZ object files, possibly converting formats as well.
vinrz-elf-gdb	Debugger for the VinRZ target, needs a backend such as simulator or emulator.
vinrz-elf-run	Provides a simulator backend for vinrz-elf-gdb.
libc.a	ANSI C runtime library.
libm.a	C mathematical subroutine library.

Open Virtual Platforms (OVP)

Virtual platforms are the foundation for the next generation of software development environments, especially for those with multiple cores. Open Virtual Platform (OVP) is a Virtual Platform, which provides libraries of processor and behavioral models, and APIs for building custom processors, peripherals and platforms. This is just what is needed to use existing models or build custom models, and OVP is easy to use, open and flexible.

The focus of OVP is to accelerate the adoption of the new way to develop embedded software - especially for SoC and MPSoC platforms. Adopting Virtual Platforms enables earlier development and testing of software, dramatically reducing SoC schedules and should significantly reduce initial development and maintenance costs for embedded software.

VinChip Systems has adopted OVP's morphing technology to develop an simulation model for its processor VinRZ5110. It runs under OVPSim Windows platform.

VinRZ5110 Processor Model and User Guide are available for download from the OVP Library page under the following links.

http://www.ovpworld.org/library/wikka.php?wakka=VinRZ5110 
http://www.ovpworld.org/library/wikka.php?wakka=VinRZ5110ModelUserGuide