VERIFICATION IPs

VERIFICATION IPs

The Vinchip’s USB Verification IP (VIP) for USB is a complete VIP solution for the Universal Serial Bus Revision 2.0, 3.0, 3.2 Specification. It provides a mature and comprehensive verification IP (VIP) for the USB protocol, which is part of the USB family. Incorporating the latest protocol updates, the USB VIP is not only a complete bus functional model for the DUT but it also provides integrated automatic protocol checks and coverage model. USB VIP is designed to make it easy for you to integrate in testbenches for IP, system-on-chip (SOC), and sub-system level. The USB VIP helps you to reduce time to test by accelerating verification closure and ensuring end product quality. The Verification IP for USB runs on all major simulators and supports all main verification languages, such as Verilog, System Verilog, alongside industry-standard methodologies for testbench writing, such as Universal Verification Methodology (UVM).

Product Highlights

Generation of constraint-random bus traffic

Built-in verification plan, protocol checks, and coverage model

Support for trace debug capability, packet tracker, and waveform debugger

Key Features:

Speed Configurations

Gen2x2, Gen1x2, Gen2x1, and Gen1x1

Supported DUT Models

Host and Device model for USB IPs (USB 2.0, USB 3.0, USB 3.1, USB 3.2) Hub Model (3.2/3.1/3.0/2.0)

Supported Interfaces

 UTMI/UTMI+ (8 or 16-bit data width) ULPI
PIPE (8, 16, or 32-bit PIPE width)